Seeking to improve an already successful operation, a leading edge customer took into consideration its polishing process. Visionary leadership and close collaboration led to exploring new CMP - chemical mechanical planarization pad technologies as an approach to improving performance and reduce cost.
ILD CMP with Silica Abrasive Particles: Effect of Pore Size of CMP Pad on Removal Rate Profiles
The influence of pad intrinsic properties on the removal rate profiles of ILD CMP with fumed silica abrasive slurry was studied by changing pad's polymer hardness, porosity, and pore size. Of these intrinsic properties, pore size is found to be most critical to removal rate profiles. By systematically changing the pore size from <1μm to >100 μm, with porosity from 5% to 50%, of pad made of thermal-plastic urethane (TPU), removal rate profile of oxide polishing was studied. A flat removal rate profile cross wafer is desired for ILD CMP. It was found that when the pore size was larger than a certain threshold, flat removal rate profiles could be achieved. Below the threshold, severe edge-fast/center-slow removal rate profiles were observed and such profiles cannot be remedied by changing pad's other properties like porosity or polishing process conditions. A model is proposed to explain the non-flat removal rate profiles associated with the small pore size (<20 μm).
Solid state microcellular foaming (SSMF) process was used to produce porous CMP pads in a variety of pore size and porosity range, using a variety of TPU resin hardness. By controlling the pore size, porosity, and pad hardness one is able to manufacture CMP polishing pads that offer tunable pad properties. A brief introduction to SSMF manufacturing process and thereby, unique microstructures created, is first addressed, followed by inner layer dielectric (ILD) CMP polish results, describing the effects of top TPU foam sheet properties such as hardness, pore size and porosity on ILD removal rate (RR) and wafer defects. Softer TPU based porous pads showed significantly lower wafer scratch counts, while only a moderate increase in the ILD RR was seen with increasing resin hardness, for similar pore size and porosity pads. Pore size has insignificant influence on wafer defect count but has significant influence on the ILD RR profile. CMP pads made from small pore size foams cause a non-flat removal rate profile.
Simultaneous absolute determination of particle size and effective particle density of colloids using disc centrifuge photodensitometry is demonstrated in this paper.
This CMC presented paper, explores
1. An overview of Polishing Rate - What controls rate?
2. Surface analysis of polishing pad
3. Correlation of polish rate to contacts - Contact area, number, and size
4. Simulation of rate to polishing pad surface - How to predict rate from surface analysis?
In order to enable high-k metal gate technology, new chemical mechanical planarization steps or slurries are needed to meet the stringent planarity or defect requirements for device performance. This paper will describe several of these slurry technologies in detail, including poly-open-polish, Aluminum CMP, or improvements required in Tungsten polishing. The keys to these technologies are outlined or polishing performance given in detail. The critical mechanisms involved in the material polishing for each of these steps are also introduced. All of these new technologies are needed in order to build a successful high-k metal gate device for advanced node integration via a replacement gate build strategy.
Continued IC dimensional scaling requires new materials, such as ruthenium thin film barriers, for copper interconnects. Fast or reproducible chemical mechanical planarization processing of tantalum, ruthenium or copper dual-damascene interconnects have been developed. Due to the unique materials property challenges of ruthenium, both selective or relatively non-selective CMP slurry sets have been developed to work with soft pads. Through tuning slurry properties to match known topographic variations, negative dielectric dishing can be achieved.
The mechanism of haze reduction during silicon polishing using a new generation of additives has been explored. These additives are thought to decrease haze by adsorbing to the wafer surface or increasing the activation energy of the reaction or the silanolates on the silica particle surface with the surface silicon. This leads to greater selectivity or the peaks or alleys resulting in a net decrease in surface roughness.
The mechanism of oxide polishing at low pH in the presence of an organic cation is discussed. The role of the cation is thought to involve increasing the nucleophilicity of the silanolate active site on the particle surface by lowering the hydration state. Additionally, the activation energy of the reaction may be lowered by charge attraction or the particle or wafer surface or by increased hydrophobic interactions.
While it has always been important to control Large Particle Counts (LPC) in chemical mechanical planarization processes, this key process control metric has become even more important for new materials or applications. Commercially available slurries today show very low LPC levels as delivered, yet improper process conditions can create LPC due to residues as well as slurry agglomeration. Thus, data taken from as-delivered slurries are not reliable predictors of final defect counts. Tools allow for the early detection of LPC excursions, or proper process recipes or consumables sets can be optimized to prevent LPC formation. Fumed silica slurry LPC > 1469 m in diameter can be detected with dual-sensor SPOS, or binned using field-flow fractionation (FFF).
CMC's "CMP For Metal-gate Integration" article in Solid State magazine.
For over twenty years of IC manufacturing, the creation of planar device structures has required the use of technologies to reduce topographic variation. Chemical mechanical planarization (CMP) - pressing wafers into rotating pads in the presence of special slurry blends to produce removal through chemically amplified nano-scale abrasion - has become a critical part of modern IC fabrication. Click here to read the full article.