Prime polished silicon wafers are the key substrate in a wide range of advanced integrated circuit (IC) applications. Prime polished wafers are a highly refined, ultra-pure crystalline silicon with ultra-flat and ultra-clean surfaces that are custom built to meet customer specifications. Advanced technology nodes in the IC roadmap also mean more stringent demands on the silicon wafer upon which these devices will be built. Chemical mechanical polishing (CMP) processes are required to produce these silicon wafers.
There are three principle polishing steps that are required to produce a silicon wafer that can be used in IC manufacturing: edge polish, stock polish and final polish. CMC has developed a suite of slurries for each of these polishing steps that offers differentiated performance and lower cost of ownership to prime silicon wafer companies. Our slurries meet the highest standards of industry purity and work to remove surface defects and produce extremely flat, mirror-like surfaces.
The edge, as well as the surfaces of prime silicon wafers, must be polished prior to device manufacturing. Edge defects must be eliminated or the yield will be severely affected. CMC has developed a line of fully formulated, colloidally stable edge polishing slurries that offer enhanced removal rate, exceptional purity, recycle stability and excellent cost of ownership.
Silicon stock polishing is required to correct and remove the damage on the wafer surface that occurred during the wafering and grinding steps. Removal budgets of several microns are common, but the resulting surface must not have high nanotopography and micro waviness. CMC stock polishing slurries have been engineered to provide both high removal rate and low resulting nanotopography. We have also chemically formulated our colloidally stable slurries to provide excellent cost of ownership and high purity.
Often referred to as haze-free polishing, a final step polish is typically the last step in prime wafer manufacturing. Removal rate is low and the goal is a defect-free, flat surface with a mirror finish (low haze). Of extreme importance is very low trace metal contamination, as the silicon surface acts as a sponge to these metals. CMC has developed final polish slurries with proprietary chelation technology to scavenge any free trace metals that may get introduced during polishing to prevent them from absorbing into the wafer itself. In addition, our slurries offer low surface roughness and low defectivity (LPD) with favorable cost of ownership.
Reclaim wafers are used prime and test wafers that have been stripped of all films and patterns and re-polished to remove scratches. These services enable semiconductor manufacturers to gain further efficiencies through the increased re-use of silicon test wafers within their production processes. Cabot Microelectronics has developed slurries specifically designed for polishing reclaim wafers. Often times the slurry must be custom designed to work optimally with your polishing pad & tool set to meet target specifications. Let CMC tailor a slurry set that will deliver superior performance in terms of defectivity, haze, flatness, and particle count along with excellent cost of ownership.
CMC's "CMP For Metal-gate Integration" article in Solid State magazine.
For over twenty years of IC manufacturing, the creation of planar device structures has required the use of technologies to reduce topographic variation. Chemical mechanical planarization (CMP) - pressing wafers into rotating pads in the presence of special slurry blends to produce removal through chemically amplified nano-scale abrasion - has become a critical part of modern IC fabrication. Click here to read the full article.